发明名称 RECEPTION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a reception circuit which can output an exact binary signal in spite of the amplitude and the duty ratio of input signal. SOLUTION: Concerning a comparator 2, an input signal VB is inputted to one input terminal, the charging/discharging voltage of capacitor CT to be charged/discharged based on the change of a signal VB is inputted to the other input terminal as a threshold VTH and by comparing the signal VB with the threshold value VTH, an output signal VX binarizing the input signal VB is outputted. A 1st switch SW1 is interposed between the capacitor CT and a high potential side power source V1, and a 2nd switch SW2 is interposed between the capacitor CT and a low potential side power source V2. When an input signal voltage gets higher than the threshold VTH more than a prescribed value, the 1st switch SW1 is turned on by a control circuit 3 so as to charge the capacitor CT with the power source V1 and when the input signal voltage gets lower than the threshold value VTH more than the prescribed value, the 2nd switch SW2 is turned on so as to discharge the electric charges of the capacitor CT with the power source V2.
申请公布号 JPH10294650(A) 申请公布日期 1998.11.04
申请号 JP19970104409 申请日期 1997.04.22
申请人 FUJITSU LTD;FUJITSU VLSI LTD 发明人 NISHIZONO KAZUNORI;FUNAKI TETSUJI
分类号 H03K5/08;H03F3/08;H04B10/07;H04B10/40;H04B10/50;H04B10/516;H04B10/556;H04B10/60;H04B10/61;H04B10/69 主分类号 H03K5/08
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