发明名称 METHOD AND APPARATUS FOR OPTIMIZING SEMICONDUCTOR DEVICE USING ON-CHIP CONFIRMATION CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a method and an apparatus for optimizing a semiconductor device so as to assure functionality under all conditions of the element and improve the overall performance. SOLUTION: An on-chip optimization circuit 105 of a semiconductor device 100 provides a delay value indicating how the edge of active signal is delayed to a delay generator 120. Timing for modifying an element is generated on the basis of the delay value. Using the timing for modifying an element, an on-chip confirmation circuit 110 inspects a part of a semiconductor element 130 to evaluate functionality. It is determined whether an optimum delay value is selected or not on the basis of the functionality. When an optimum delay value is not determined, a new timing for modifying an element is generated using a new delay value, and the sequence of functionality inspection and determination is repeated until an optimum value is determined.</p>
申请公布号 JPH10294379(A) 申请公布日期 1998.11.04
申请号 JP19970311439 申请日期 1997.10.27
申请人 MOTOROLA INC 发明人 MAGUIRE JEFFREY E
分类号 G06F15/78;G01R31/30;G06F1/04;G11C29/02;H01L21/82;H01L21/822;H01L27/04;H03K19/00;(IPC1-7):H01L21/82;G11C29/00 主分类号 G06F15/78
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