CMOS process forming wells after gate formation

摘要

A substrate has defined therein one or more active regions. A layer of polysilicon is deposited and patterned to form gates for various CMOS devices. A masking layer is then deposited and selectively etched to leave exposed portions of the substrate. Dopants of a first conductivity type are implanted into the exposed portions of the substrate to form one or more well regions of the first conductivity type. Using this masking layer and the polysilicon gates left exposed thereby as a mask, dopants of a second conductivity type are then implanted into the substrate to form source and drain regions of the second conductivity type in the well regions of the first conductivity type. The masking layer is then removed. In this manner, source and drain regions may be formed using the same masking layer used to define the well within which the source and drain regions lie, thereby reducing both time and expense in the fabrication of CMOS devices.