发明名称 Process monitor test chip and methodology
摘要 A process monitor test chip and methodology allows process-related manufacturing defects to be quickly identified and isolated. A basic circuit block of a test chip having a number of inverter cells serially connected with a corresponding number of observation points before the input of each inverter cell provides for the inverter cells in the basic circuit block to be probed and thus observed by e-beam technology. Any required number of basic circuit blocks may be serially connected end to end to constitute a chain circuit. Within the test chip itself, a plurality of chain circuits may be connected serially or in parallel to accomplish different testing goals. By controlling an input signal and a control signal of a multiplexing element associated with each chain circuit, the plurality of chain circuits can be forced into a serial connection or a parallel connection. In a serial mode, the plurality of chain circuits are serially connected with one input signal and one output signal of the test chip; the serial connection may be used during burn-in of the test chip to test for whether the test chip contains any process-related manufacturing defects. Once it has been determined that the test chip does contain process-related manufacturing defects, the parallel connection allows the defects of the test chip to be quickly isolated.
申请公布号 US5831446(A) 申请公布日期 1998.11.03
申请号 US19960679138 申请日期 1996.07.12
申请人 STMICROELECTRONICS, INC. 发明人 SO, JASON S.;LE, TAM T.;ASNANI, MILIND
分类号 H01L23/544;(IPC1-7):G01R31/28 主分类号 H01L23/544
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