| 摘要 |
A multiplier core circuit using four transistors, in which a novel input voltage combination is adopted. This circuit contains first, second, third and fourth bipolar transistors or field-effect transistors whose emitters or sources are coupled together. Collectors or drains of the first and second transistors are coupled together to form an output end and collectors or drains of the third and fourth transistors are coupled together to form the other output end. An output signal of the circuit is differentially taken out from the output ends. The first to fourth transistors are applied with first to fourth voltages at their base or gate. The first, second, third and fourth voltages are [-Vx+(+E,fra 1/2+EE )Vy], (Vx+Vy), (-Vx+Vy) and [Vx+(+E,fra 1/2+EE )Vy], respectively. These four voltages may be (Vx-Vy), 2Vx, Vx and (2Vx-Vy), respectively. If a, b and c are positive constants, these four voltages may be expressed as (aVx+bVy), [(a-c)Vx+(b-1/c)Vy], [(a-c)Vx+bVy], and [aVx+(b-1/c)Vy], respectively.
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