发明名称 |
Resolving processor and system bus address collision in a high-level cache |
摘要 |
A L2 cache for resolving collisions between processor request originating from a processor and system request originating from a computing unit attached to the system bus is provided. First, the L2 cache snoops a system request to access a shared resource. This shared resource is often an area of main memory contained in the L2 cache. Next, the L2 cache receives a processor request to access the shared resource also. The L2 cache will delay sending an acknowledge signal to the processor. The L2 cache then makes a determination as to whether the address and system request type must be sent to the processor. If data associated with the system request would alter a line in a L1 cache associated with the processor, a retry signal is sent to the processor. If the system request would not alter a line in the L1 cache, the L2 cache will wait until the system request finishes accessing the shared resource to process the processor request, thereby avoiding the sending of a retry signal to the processor.
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申请公布号 |
US5832276(A) |
申请公布日期 |
1998.11.03 |
申请号 |
US19960726947 |
申请日期 |
1996.10.07 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
FEISTE, KURT ALAN;SOMYAK, THOMAS J. |
分类号 |
G06F12/08;(IPC1-7):G06F13/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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