发明名称 |
Clock signal generating apparatus and clock signal generating method |
摘要 |
An apparatus and method for generating a clock signal phase-locked to a horizontal synchronization signal of a digital video signal in which noise superposed on the horizontal synchronization signal is eliminated or reduced. To eliminate or reduce such noise, a noise suppressing device located prior to a phase comparator may be utilized. Such noise suppressing block may include a slice circuit and/or a spike removing circuit.
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申请公布号 |
US5831683(A) |
申请公布日期 |
1998.11.03 |
申请号 |
US19970806915 |
申请日期 |
1997.02.26 |
申请人 |
SONY CORPORATION |
发明人 |
MATSUMOTO, HIROAKI;UKAI, MANABU |
分类号 |
H04N5/06;H04N5/12;H04N5/21;H04N5/907;(IPC1-7):H04N5/21 |
主分类号 |
H04N5/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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