发明名称 Variable size redundancy replacement architecture to make a memory fault-tolerant
摘要 A variable size redundancy replacement (VSRR) arrangement for making a memory fault-tolerant. A redundancy array supporting the memory includes a plurality of variable size redundancy units, each of which encompasses a plurality of redundancy elements. The redundancy units, used for repairing faults in the memory, are independently controlled. All the redundancy elements within a repair unit are preferably replaced simultaneously. The redundancy elements in the redundancy unit are controlled by decoding address lines. The variable size that characterizes this configuration makes it possible to choose the most effective redundancy unit, and in particular, the one most closely fitting the size of the cluster of failures to be replaced. This configuration significantly reduces the overhead created by added redundancy elements and control circuitry, while improving the access speed and reducing power consumption. Finally, a fault-tolerant block redundancy controlled by a priority decoder makes it possible to use VSRR units for repairing faults in the block redundancy prior to its use for replacing a defective block within the memory.
申请公布号 US5831914(A) 申请公布日期 1998.11.03
申请号 US19970825949 申请日期 1997.03.31
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 KIRIHATA, TOSHIAKI
分类号 G11C29/04;G11C29/00;(IPC1-7):G11C7/00 主分类号 G11C29/04
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