Inter-chip bus with equal access between masters without arbitration

摘要

A computer system, comprising a first expansion bus which operates according to a first transfer protocol. The first expansion bus is adapted to couple to one or more peripheral devices. A central processing unit and a bus bridge are operatively coupled to the first expansion bus. A second bus including a second transfer protocol is coupled to the bus bridge. A plurality of peripheral devices compatible with the second transfer protocol is coupled to the second bus. The bus bridge is configured to communicate with the plurality of peripheral devices in a round-robin ping-pong fashion. The bus bridge is configured to generate address/data pairs to at least one port of one of the peripheral devices, and thereafter receive address/data pairs from the one port of the peripheral device. The bus bridge is configured to generate and receive address/data pairs sequentially to ports in at least a subset of the plurality of peripheral devices in a round robin fashion.