发明名称 |
Method and apparatus for performing cyclic redundancy check synchronization |
摘要 |
A method and apparatus for synchronizing and error checking received bitstreams of encoded information is provided. The apparatus includes a single polynomial division shift register. The method involves calculating successive syndromes using the single polynomial division shift register by shifting the received bits of information, generating a syndrome, and comparing the syndrome to a known marker syndrome.
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申请公布号 |
US5832031(A) |
申请公布日期 |
1998.11.03 |
申请号 |
US19950516584 |
申请日期 |
1995.08.18 |
申请人 |
HUGHES ELECTRONICS CORPORATION |
发明人 |
HAMMONS, JR., A. ROGER |
分类号 |
H04L1/00;(IPC1-7):H04L5/12;H04L23/02 |
主分类号 |
H04L1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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