| 摘要 |
The first bus (11) and the second bus (12) are interconnected via the bus repeater (13) having a buffer memory, with DMA (direct memory access) controllers (22, 27) connected to respective buses (11 and 12). The bus repeater (13) can send DMA requests to the DMA controllers (22, 27), and the CPUs (21, 26) can mask these DMA requests. The DMA controller (22) DMA-transfers data on the bus (11) to and from the buffer memory in the bus repeater (13). The DMA controller (27) DMA-transfers data between the buffer memory and the bus (12). The CPU (21) can mask the DMA request from the bus repeater (13) and directly accesses the buffer to check the DMA function. This facilitates debugging of a system to be DMA-transferred between different buses through the buffer.
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