| 摘要 |
<p>A compositing buffer (601) having an adjustable size and configuration reduces complexity and size of a multimedia processor integrated circuit. The compositing buffer (601) may be optimized for lower resolutions, thus reducing its overall size and complexity, while still providing support for higher resolutions which may be required to support a particular standard. A pixel mapping logic (602) receives data indicating the number of lines per band and number of pixels per line, as well as color depth (or any two of these data) and correctly maps compositing RAM bank access requests to the correct pixel location.</p> |
