发明名称 Apparatus and method for resolving dependencies among a plurality of instructions within a storage device
摘要 <p>An apparatus and method for resolving data dependencies among a plurality of instructions within a storage device, such as a reorder buffer in a superscalar computing apparatus employing pipeline instruction processing. The storage device has a read pointer, indicating a most recently-stored instruction and has a write pointer, indicating a first-stored instruction of the plurality of instructions within the storage device. A compare-hit circuit generates a compare-hit signal upon each concurrence of the respective source indicator in a next-to-be-dispatched instruction with the destination indicator of an earlier-stored instruction within the storage device; a first enable circuit generates a first enable signal for a first packet of instructions defined by the read pointer and the write pointer; a first comparing circuit generates a hit-enable signal for each concurrence of the compare-hit signal and the first enable signal; a second enable circuit generates a second enable signal for a second packet of instructions defined by the read pointer and the hit-enable signal; and a second comparing circuit generates the output signal for each concurrence of the second enable signal and the hit-enable signal. <IMAGE></p>
申请公布号 EP0533337(B1) 申请公布日期 1998.10.28
申请号 EP19920307185 申请日期 1992.08.06
申请人 ADVANCED MICRO DEVICES, INC. 发明人 TRAN, THANG MINH
分类号 G06F5/10;G06F5/12;G06F7/74;G06F9/38;(IPC1-7):G06F9/38 主分类号 G06F5/10
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