| 摘要 |
<p>A semiconductor integrated circuit includes upper level and lower level substrate interconnection layers which are positioned in a scribing line area and which are separated from each other an interlayer insulating film formed therebetween. For planarization, an upper surface of the interlayer insulating film is coated with an SOG silicon oxide insulating film formed by coating an SOG organic solution by means of a spin coating. The lower level substrate interconnection layer is divided into a plurality of segments separated from each other by gaps which are provided at a plurality of different locations and which allow the SOG organic solution to escape through the gaps by a centrifugal force when the SOG organic solution is applied by the spin coating. The upper level substrate interconnection layer is electrically connected to the plurality of segments of the lower level substrate interconnection layers through contacts hole formed to penetrate through the interlayer insulating film. <IMAGE></p> |
