| 摘要 |
<p>A test mode of a memory device may be invoked that varies the sense amplifier clocking of the memory device as a function of manipulation of a control signal external to the memory device. At the appropriate logic state of a test mode enable signal, the test mode of the memory device is entered. Normal clocking of the sense amplifier is suspended during the test mode and the sense amplifier is clocked according to the transition of an external control signal from a first logic state to a second logic state. A predetermined period of time after the transition of the external control signal, the sense amplifier if clocked. <IMAGE></p> |
