A coupler circuit for directing data exchanges between a cache memory, a disk controller and an MCA bus

摘要

An integrated coupler circuit for relieving a microprocessor of directing individual data exchanges between a cache memory, composed of a dynamic read/write memory, and a disk controller and an MCA bus. The integrated coupler circuit provides a means for directing data exchanges between the disk controller and the dynamic cache memory with the highest level of priority after initialization by the microprocessor, refreshing the dynamic cache memory with the second highest level of priority, directing data exchanges between the microprocessor and the dynamic cache memory with the third highest level of priority, and directing data exchanges between the dynamic cache memory and a stack incorporated into the coupler circuit with the lowest level of priority after initialization by the microprocessor.