Viterbi decoder circuit

摘要

A Viterbi decoder circuit for decoding an encoded data signal containing Viterbi branch metric information includes a configurable memory which is alternately configured to have four stages of memory in which the incoming data signal is stored and selectively read out based upon Viterbi trellis address information contained therein. While the present data of the incoming data signal is being stored in one memory stage, individual bits from selected bytes of previously stored incoming data are read out from a second memory stage and used to form the next address for the second memory stage and an address for a third memory stage from which further previously stored incoming data are read out and decoded to form the final Viterbi-decoded data. Starting from an arbitrarily selected initial address within the second memory stage, each bit which is read out contains address information corresponding to a Viterbi trellis address and determines the next address within the second memory stage from which the next bit is to be read.