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发明名称
METHOD OF FLATTENING INTERMETALLIC DIELECTRIC BETWEEN MULTILEVEL MUTUAL CONNECTION ON INTEGRATED CIRCUIT
摘要
申请公布号
JPH10289953(A)
申请公布日期
1998.10.27
申请号
JP19980075647
申请日期
1998.03.24
申请人
IND TECHNOL RES INST
发明人
LOU CHINE-GIE
分类号
H01L21/3105;H01L21/316;H01L21/768;H01L23/522;(IPC1-7):H01L21/768
主分类号
H01L21/3105
代理机构
代理人
主权项
地址
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