| 摘要 |
PROBLEM TO BE SOLVED: To display a smoothly moving image and to reduce the hardware quantity of the decode part by decoding image data encoded at a 1st frame rate and specifying timing to start decoding when outputting the data at a 2nd frame rate lower than the 1st one. SOLUTION: AND gates 111-113 and an OR gate 114 are functioned as a selector circuit. Namely, when a field count value is '1' or '6', a delay field synchronizing signal or when the field count value is '2' or '7' or when it is '4' or '9', an A or B detecting signal, which is to be made active when a picture term value is equal with a predetermined specified value A or B, is outputted as a decode timing signal. Thus, since two pictures are displayed just for one field during the period of 10 fields, frame rate conversion can be performed for processing six pictures P1-P6 during the period of 10 fields, namely, during the period of 5 frames. |
