发明名称 Implementation efficient digital picture-in-picture decoding methods and apparatus
摘要 An implementation efficient video decoder suitable for use as a picture in picture decoder is described. In one embodiment, the video decoder receives primary and secondary bitstreams with the secondary bitstream including the video data intended to be displayed as inset pictures. The decoder uses many of the same circuit components on a time shared basis to decode both the main and inset pictures reducing the amount of circuitry required to implement the decoder. In one embodiment a preparser discards the majority of DCT coefficients in the secondary bitstream and the remaining data is variable length decoded and then variable length encoded using a non-MPEG compliant coding scheme prior to storing the inset picture data in a coded data buffer. Re-encoding of the selected inset picture data in this manner greatly reduces data storage requirements and simplifies the circuitry required to subsequently decode the inset picture data. To reduce frame memory requirements inset picture data is downsampled, stored and then upsampled prior to display thereby reducing inset picture frame memory buffer requirements.
申请公布号 US5828421(A) 申请公布日期 1998.10.27
申请号 US19950468147 申请日期 1995.06.06
申请人 HITACHI AMERICA, LTD. 发明人 BOYCE, JILL MACDONALD;PEARLSTEIN, LARRY;LANE, FRANK ANTON
分类号 G06T3/40;G06T9/00;H04N5/44;H04N5/45;H04N5/46;H04N7/24;H04N7/26;H04N7/36;H04N7/46;H04N7/50;(IPC1-7):H04N5/445 主分类号 G06T3/40
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