| 摘要 |
A clock failure detection circuit which monitors a clock by comparing the clock to at least one delayed version of itself is provided. The original clock and the delayed version will be offset, such that an edge of one of them can clock a logic circuit to determine if the clock is at the proper level. By setting up the delay so that a clock edge is generated when the clock signal should be low, for instance, a bad output signal will be provided whenever the clock is high instead. This could be caused by the clock being stuck high, or by an irregular pulse width.
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