| 摘要 |
PROBLEM TO BE SOLVED: To make it possible to form an interconnection having high reliability by readily and effectively relaxing the step difference between adjacent regions in a semiconductor substrate. SOLUTION: A polysilicon film FG for relaxing step differences is provided on a field oxide film 12 in a peripheral circuit portion PC, a lower side, along the boundary between a memorial cell array portion MA and the peripheral circuit portion PC, to considerably mitigate the step difference at the boundary between both regions MA and PC (PCA), resulting in a considerable relaxation or reduction of the global step difference in a BPSG layer 38. Accordingly, the global step difference in the vicinity of the boundary is rendered gentle and small, and therefore, exposure or processing of a photoresist at the time of photolithography can be performed in accordance with a designed pattern in the steps of making an interconnection. In addition, there is no occurrence of short circuiting and disconnection between the individual interconnections formed on the BPSG layer 38. Further, because the polysilicon film FG for mitigating step differences is connected to a ground potential, there is no risk of generation of coupling noises. |
