| 摘要 |
PROBLEM TO BE SOLVED: To enable high integration and speed up, while adopting a split word line system by supplying an N-type well region with constant voltage outputted from the source of a MOSFET for voltage clamping, as a bias voltage. SOLUTION: Main word driver regions 12 are made above and below a main low decoder provided at the vertical center to the longitudinal direction, and the main word lines of upper and lower memory array are driven, and the memory array 15 is surrounded by a sense amplifier region 16 and a sub- word driver region 17. For the sense amplifier activating signals supplied to the gate of a first power MOSFET, the pulse width is set by a delay time made by a delay circuit. Hereby, the operation timing of the sense amplifier can be set without being affected by the ripple of the power voltage. Accordingly, it and the stabilization of the amplifying action of the sense amplifier act multiplicatively, and the reduction in the memory access time becomes possible. |
