| 摘要 |
PROBLEM TO BE SOLVED: To shorten the logic simulation execution time and the verification time of the logic simulation result, to reduce the number of test patterns, and to detect a fault of a counter by increasing the speed of access to an external device at the time of logic simulation and test pattern generation. SOLUTION: This circuit is provided with a test signal 108 which is made effective only at the time of logic simulation and test pattern generation; and at the time of logic simulation and test pattern generation, enable signals 109 and 110 are given to cascaded counters 103 and 104, and the access to an external device 119 is terminated by the result of AND between carry signals 111 and 112 of counters 103 and 104. |
