| 摘要 |
PROBLEM TO BE SOLVED: To stabilize an operation, and speed up the access time of, for example, a synchronous SRAM containing a burst counter by performing the shift operation of a shift register selectively depending on whether a burst mode is linear or interleave sequence. SOLUTION: When a synchronous SRAM is set to a normal operation mode, only the initial setting of flip flops FF1-FF4 is performed by an internal clock signal BBC in a burst counter BC and a shift register is not shifted by an internal clock signal CBC. Therefore, predecode signals /a0/a1, a0/a1, /a0a1, a0a1 corresponding to a column being specified by address signals A0-A1 are set to a high level during one cycle. A signal path until the predecode signals are formed is the same regardless of an operation mode and a transfer delay time difference between the operation modes is small, thus preventing a hazard against the predecode signal from being generated and speeding up an access time.
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