RESAMPLING CIRCUIT AND CONTROL METHOD THEREFOR

摘要

PROBLEM TO BE SOLVED: To provide a digital signal processing circuit that is adaptive to versatility of available input data transmission rates like a 2-stage resampling. SOLUTION: This resampling circuit 20 has a polyphase Finite Impulse Response(FIR) interpolator 30, a multi-term interpolator 31 with a sample input connecting to a sample output of the polyphase interpolator 30 and a numerically controlled oscillator(NCO) 32 that has an Nc integral bit output connecting to a control input of the FIR interpolator 30 and an Nf fraction bit output connecting to a control input of the multi-term interpolator. The circuit also has a reference clock oscillator 33. The NCO(numerical control oscillator) 32 has a sample clock generator that generates a sample clock signal based on a reference clock signal and the FIR interpolator 30 has a sample clock input that receives the sample clock signal from the sample clock generator. The multi-term interpolator 31 has an input that applies clocking to an output sample connecting to the reference clock 33 and an output sample from the multi-term interpolator 31 is subject to clock-out, based on the reference clock signal.