| 摘要 |
PROBLEM TO BE SOLVED: To provide a high speed sigma delta A/D converter for a sequence of an analog sample xn . SOLUTION: This A/D converter is provided with a plurality of sample-and- hold circuits 40n each having one input receiving an analog sample xn and receiving (N-1) sets of phase clocksϕn , sampling and holding the corresponding analog sample xn depending on the input and each phase clockϕn , (N-1) stages of circuit stages and a D/A converter that providing a quantization sum signal yN-1 to a preceding sum signal input of a 1st stage adder 421 . Each circuit stage (n) has an adder 42n and a quantizer 44n . Each adder 42n has a data input that receives a data signal xn from a corresponding sample-and-hold circuit 40n , a preceding summing signal (Wn-1 ) input and an inverting input of a preceding quantization signal (yn-1 ) and produces a sum signal (Wn =xn +Wn-1 -yn- ) as an adder output. The quantizer 44n connects to an output of a corresponding adder and quantizes a sum signal wn to produce a quantized sum signal yn .
|
