发明名称 |
TWO-INPUT ADDER WITH CORRECTION AND MULTIPLIER |
摘要 |
PROBLEM TO BE SOLVED: To prevent the increase of a gate stage number based on the addition of the correction term of a highest digit by providing a means for obtaining carry propagation to respective bits in the case that a carry signal and the correction term are both '1'. SOLUTION: A carry look-ahead auxiliary means 4 generates carry input generated in the respective bits when the carry signal C and the correction term H both take a value '1' from the carry signal C, the correction term H and the output of a PG generation means 1. A double carry detection means 5 detects whether or not the two pieces of carries are generated because the carry signal C and the correction term H simultaneously take the value '1'. A sum generation means 6 obtains and outputs the sum of the two sets of input signals A and B, the carry signal C and the correction term H by obtaining the exclusive OR of the output of a temporary sum generation means 2 and the output of the double carry detection means 5 and obtaining the exclusive OR of the OR of the output of a carry look-ahead means 3 and the output of the carry look-ahead auxiliary means 4 and the output of the exclusive OR. |
申请公布号 |
JPH10283163(A) |
申请公布日期 |
1998.10.23 |
申请号 |
JP19970089155 |
申请日期 |
1997.04.08 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
TAGAMI KAZUFUMI |
分类号 |
G06F7/50;G06F7/508;G06F7/52;G06F7/523 |
主分类号 |
G06F7/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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