发明名称 CLOCK SIGNAL DRIVING CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a larger power saving effect by deciding and supplying the combination of an operation frequency and a drive current capable of operating system logic. SOLUTION: A frequency control circuit 1 decides a frequency to be supplied to the system logic and reports it to a frequency variable oscillation circuit 2 by using control signals (a). For the decision method of the frequency, an operation is performed by a maximum frequency capable of operating the system logic at the time of a normal operation, and at the time of wanting to reduce power consumption, at the time of using a battery for instance, the system logic is operated at a low frequency. Simultaneously, a drive current decision circuit 3 decides a minimum drive current capable of operating the system logic at the frequency decided in the frequency control circuit 1 based on the control signals (a). The drive current decided by the drive current decision circuit 3 is reported to a drive circuit 4 by the control signals (c), and by turning parallelly connected transistors on and off, only a required current is driven.</p>
申请公布号 JPH10283056(A) 申请公布日期 1998.10.23
申请号 JP19970087942 申请日期 1997.04.07
申请人 NEC CORP 发明人 YAMASHITA TOSHITSUGU
分类号 G06F1/04;H03K5/02;H03K19/00;(IPC1-7):G06F1/04 主分类号 G06F1/04
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