发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To attain the sharing of the time constant of an LPF(low pass filter) against the frequency that is outputted from a PLL circuit by preparing plural modes where a variable dividing device which outputs a reference signal via a reference oscillator and also divides the output of a VCO(voltage controlled oscillator) performs the division with a specific division ratio. SOLUTION: A variable dividing device 4 variably divides the output of VCO 1 and 2 with a division ration 1/A (A: a >=2 integer), and a reference oscillator 5 selectively outputs a 1st reference signal and a 2nd reference signal having the frequency equal or approximate to that of the 1st reference signal. An LPF 7 converts the output of a phase comaprator 6 which compares the reference signal of the oscillator 5 with the output of the device 4 into the control voltage with a time constant shared by the reference signal. Then a control circuit 8 prepares a mode where the 1st reference signal is outputted from the oscillator 5 and the device 4 performs the division with a B/A division ratio and another mode where the 2nd reference signal is outputted from the oscillator 5 and the device 4 performs the division with a C/A division ratio (B, C: positive integers).
申请公布号 JPH10285026(A) 申请公布日期 1998.10.23
申请号 JP19970081462 申请日期 1997.03.31
申请人 SANYO ELECTRIC CO LTD;TOTTORI SANYO ELECTRIC CO LTD 发明人 WASHIMI IKUAKI
分类号 H03L7/183;H03L7/093;H03L7/197;H04B1/26 主分类号 H03L7/183
代理机构 代理人
主权项
地址