| 摘要 |
PROBLEM TO BE SOLVED: To provide a digital PLL circuit small in jitter width and fast in lead-in speed in the initial operation. SOLUTION: A counter 2 starts counting an output clock CLKout when an initializing flag keeps '0' after releasing resetting and outputs a count. When a rise detector 1 detects rising of a first reference clock CLKref after releasing resetting, the detector 1 initializes the count into a count of a 3rd range and sets the initializing flag into '1' from '0'. According to this operation, the count is set to the 3rd range at the detection of the rise of a succeeding reference clock CLKref, the rise of the reference clock CLKref reaches a count M1 or M2 by a difference between the reference clock CLKref and the precision of an oscillator 5 affected on the output clock to synchronize the reference clock CLKref with the output clock CLKref. |
