Halbleiterspeichereinrichtung und Verfahren zur Fehlerkorrektur

摘要

A semiconductor memory device having a redundant circuit for electrically replacing a defective memory cell column with a spare memory cell column. An electric fuse (25) is connected between a precharging voltage line (VBL) and bit lines (BL, &upbar& B). When a defective memory cell exists, the precharging voltage tries to vary through this fuse. However, this fuse is cut off, so that the precharging voltage is prevented from varying. Accordingly, data stored in the remaining memory cells are read out correctly and without delay.