Formation of interconnects in semiconductor device between different level wiring lines

摘要

Forming an interconnect in a semiconductor device comprises: (a) providing a conductive layer adjacent a first insulating layer above a semiconductor substrate; the two layers have coplanar upper surfaces; (b) depositing an etch stop layer, different from the first insulating layer, on the upper surfaces of the two layers; (c) depositing a second insulating layer, different from the etch stop layer, on the etch stop layer; (d) etching a via to expose a portion of the etch stop layer, the etched via is formed at least partially above the conductive layer; (e) removing the etch stop layer within the via; (f) depositing a glue layer on the conductive layer within the via; and (g) filling the via with a conductive material. Also claimed is a similar method of forming an interconnect comprising: providing an insulating layer (30) over a semiconductor substrate (10); forming a pattern of depressions in the insulating layer; depositing a metal layer over the insulating layer; planarising the metal layer to form a pattern of first level metal wiring lines (32) within the insulating layer corresponding to the pattern of depressions; depositing an etch stop layer (34) on surfaces of the insulating layer and the metal wiring lines; depositing a dielectric layer (36) over the etch stop layer; etching a via through the dielectric layer to expose the etch stop layer; removing the etch stop layer within the via to expose at least a portion of a metal wiring line; depositing a glue layer on the metal wiring line within the via; and forming a metal plug (42) within the via.