发明名称 Reprogrammable state machine and method therefor
摘要 A reprogrammable state machine which allows the state flow and control outputs to be reprogrammed without requiring modification of the state machine. The reprogrammable state machine uses a reprogrammable logic unit to generate the state transitions and output transitions for each state of the reprogrammable state machine. A memory control unit is used to program the state machine reprogrammable logic unit with default settings for the state transitions and output transitions for each state of the reprogrammable state machine. The memory control unit is also used to reprogram the state machine reprogrammable logic unit with modified settings for the state transitions and output transitions for each state of the reprogrammable state machine which needs to be modified.
申请公布号 US5825199(A) 申请公布日期 1998.10.20
申请号 US19970792712 申请日期 1997.01.30
申请人 VLSI TECHNOLOGY, INC. 发明人 SHELTON, ROGER;CHAMBERS, PETER
分类号 H03K19/173;(IPC1-7):H03K19/173 主分类号 H03K19/173
代理机构 代理人
主权项
地址