| 摘要 |
A speculative instruction queue for a superscalar processor of the type having a variable byte-length instruction format, such as the X86 format, is organized as a 16-byte FIFO. The head of the queue is always the beginning byte of an X86 instruction, and the queue always shifts by one or more X86 instruction boundaries as X86 instructions are decoded and dispatched. Each byte position within the queue includes a valid bit for indicating whether the byte position within the queue contains valid information, the raw X86 instruction byte as originally fetched from an instruction source and stored within a preceeding cache, and a group of predecode bits assigned to the raw X86 instruction byte when initially pre-fetched and cached, and which predecode bits indicate the starting byte, ending byte, and the opcode byte of an X86 instruction, as well as the number of internal RISC-like operations into which the corresponding X86 instruction is mapped. Each byte position further includes a branch marker bit for indicating whether the byte is the last byte of a predicted-taken X86 branch instruction, and a column field to facilitate correction of a mis-predicted branch by directly indicating which column of a preceeding set-associative cache contains the mis-predicted branch instruction byte.
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