发明名称 Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices
摘要 A programmable logic array integrated circuit has several regular columns of programmable logic circuitry and a spare column which includes a subset of the programmable logic circuitry that is included in a regular column. In the event of a defect in the circuitry in a regular column that is duplicated in the spare column, the regular column logic functions that are thus duplicated are shifted from column to column so that the spare column circuitry is put to use and the defective regular column circuitry is not used. Regular column functions that are not duplicated in the spare column are not shifted. Data for programming the columns is selectively routed to the columns with or without column shifting, depending on whether that data is for functions that are or are not duplicated in the spare column.
申请公布号 US5825197(A) 申请公布日期 1998.10.20
申请号 US19960742770 申请日期 1996.11.01
申请人 发明人
分类号 G06F11/20;G06F15/78;H03K19/177;(IPC1-7):H03K19/003;H03K19/173 主分类号 G06F11/20
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