COLUMN REDUNDANCY IN SEMICONDUCTOR MEMORIES COLUMN REDUNDANCY IN SEMICONDUCTOR MEMORIES

摘要

This invention describes a column redundancy method and apparatus in a DRAM that minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required in repairing faulty columns. The invention discloses a DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address appli ed thereto, normal column drivers for energizing appropriate memory elements in res ponse to the decoder memory addresses received at an input thereof; redundant column d rivers; and switch means for selectively connecting the redundant column driver into a s elected normal driver path.