发明名称 Low temperature via and trench fill process by means of CVD of Cu followed by PVD of Cu
摘要 The disclosure relates to a process for providing complete via a trench fill on a substrate.The planarization of Cu layers forms continuous, void-free contacts or vias in sub-half micrometer applications. A refractory layer (12) is deposited onto a substrate having high aspect ratio contacts or vias (14) formed thereon. A CVD Cu layer (22) is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD Cu. Next, a PVD Cu (23) is deposited onto the previously formed CVD Cu layer at a temperature below that of the melting point temperature of Cu. The resulting CVD/PVD Cu layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Cu layer. The via fill process of the present invention is also successful with air-exposure between the CVD Cu and PVD Cu steps.
申请公布号 EP0856884(A3) 申请公布日期 1998.10.14
申请号 EP19980300539 申请日期 1998.01.27
申请人 APPLIED MATERIALS, INC. 发明人 CHEN, LIANG-YUH;MOSELY, RODERICK CRAIG;CHEN, FUSEN;TAO, RONG;GUO, TED
分类号 H01L21/285;H01L21/3205;H01L21/768;H01L23/52 主分类号 H01L21/285
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