发明名称 |
Dual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cache |
摘要 |
A microprocessor architecture including a first cache memory disposed on-chip for storing data along with an associated on-chip tag memory. A second memory is provided on-chip for storing data in a first mode of operation and for storing tags relating to the contents of a second cache memory in a second mode of operation. The mode of operation is set by control logic. The mode is selected by setting a bit in a mode control register. When the bit is set, the control logic changes the system from a first mode in which the second memory serves as additional on-chip cache memory to a second mode in which the second memory stores tags for an external level 2 cache memory. The invention provides a flexible cache structure in which increased on-chip cache is provided or tag memory area is provided for an off-chip level 2 cache.
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申请公布号 |
US5822755(A) |
申请公布日期 |
1998.10.13 |
申请号 |
US19960591921 |
申请日期 |
1996.01.25 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
SHIPPY, DAVID |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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