摘要 |
A floating gate (FG) of a ferroelectric transistor (FTR11) and a source (SS) of a selecting transistor (STR11) are interconnected. A control gate (FCG) of the ferroelectric transistor (FTR11) is connected to a word line (WL1), a drain (SD) of the selecting transistor (STR11) is connected to a bit line (BL11), and a gate (SG) of the selecting transistor (STR11) is connected to a gate line (G). In the writing mode, "5V" is given to the gate line (G) to set the selecting transistors (STR11, . . . ) to the on state. A ferroelectric layer (FM) is polarized by giving a suitable voltage to the word lines (WL1, . . . ) and the bit lines (BL1, . . . ). In the operation mode, "0V" is given to the gate line (G) to set the selecting transistors (STR11, . . . ) to the off state.
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