发明名称 |
Clock generator for a microprocessor having a delay equalization circuit |
摘要 |
A clock generator of the present invention comprises a first buffer receiving a first clock, a second buffer receiving a second clock having a amplitude being different of that of the first clock, phase comparator comparing phases between an output of the first buffer and an output of the second buffer, and means for adapting a delay time of the first buffer to a delay time of the second buffer.
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申请公布号 |
US5822573(A) |
申请公布日期 |
1998.10.13 |
申请号 |
US19960724826 |
申请日期 |
1996.10.02 |
申请人 |
NEC CORPORATION |
发明人 |
SAEKI, TAKANORI;FUKUZO, YUKIO |
分类号 |
H03L7/093;G06F1/10;G06F1/12;H03L7/08;(IPC1-7):G06F1/04 |
主分类号 |
H03L7/093 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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