发明名称 |
Clock signal frequency multiplier |
摘要 |
The invention relates to a clock signal frequency multiplier circuit. The circuit multiplies the speed of a clock signal of an integrated circuit (IC) by a factor N to generate a times-N clock signal. The circuit first receives a clock signal. Next, the circuit replicates the clock signal into a plurality of N component signals. Each Jth component signal is delayed from the (J-1)th component signal by 1/N cycles, where J equals 1 to N. The (J=1)th component signal is the clock signal. The N component signals are referred to as phase-shifted components. Finally, the circuit logically combines the phase-shifted components into a times-N clock signal.
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申请公布号 |
US5821785(A) |
申请公布日期 |
1998.10.13 |
申请号 |
US19960691765 |
申请日期 |
1996.08.02 |
申请人 |
ROCKWELL INT'L CORP. |
发明人 |
GLASS, KEVIN W.;HESHAMI, MEHRDAD |
分类号 |
H03K5/00;H03K19/21;H03L7/08;H03L7/081;H03L7/089;H03L7/16;(IPC1-7):H03B19/00 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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