SEMICONDUCTOR MEMORY AND DATA PROCESSING DEVICE

摘要

PROBLEM TO BE SOLVED: To prevent timing deviation from an external clock signal by frequency-dividing a clock signal by a frequency dividing circuit and supplying it to each parts, reducing power consumption by reducing charge and discharge currents, while providing a logic circuit synchronizing with a rising edge and falling edge of an internal clock. SOLUTION: Charge and discharge currents of a clock system are reduced to one half by frequency-dividing an external clock signal CLK into one half by a frequency dividing circuit 214 of a controller 214 and supplying an internal clock CCLK to each part. At the time, in order to avoid reducing the number of times of read-write operation into one half by one half frequency division, circuits synchronizing with both of a rising edge and a falling edge of a waveform of the CCLK signal respectively are provided, and the circuits are operated whenever the external clock CLK rises. That is, the device has constitution in which a column address buffer 205, a column address counter 207, a column decoder 203A, a sense amplifier, and a column selection circuit 203 are divided into two parts respectively.