| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a clock-tree structure using dummy buffers and dummy latches, the informing load resistances and load capacities from the clock generating circuit to the final-stage latches and realizing high-speed processing and operation in an integrated circuit. SOLUTION: In this tree structure, logic cells having small areas and the same load resistances and load capacitances as those of buffers 12, 13 and 14 and latches 15 are formed on a space on a substrate on which other elements are not formed, and used as dummy latches and dummy buffers. The dummy buffers and dummy latches are incorporated so as to make the load resistances and load capacities which differ among the paths to the final-stage latches 15 the same. Which informing the load resistances and load capacitances to all the final-stage latches, a hierarchical connection is realized. As a result, the difference between minimum delay time and maximum delay time is removed, and an increase in clock skew is prevented.</p> |
