CMOS high-speed differential to single-ended converter circuit

摘要

A CMOS differential to single-ended converter is implemented. A differential input stage comprised of a pair of N-channel transistors draws current through two fixed current P-channel load transistors. A first N-channel differential transistor provides negative feedback bias control of a current source transistor coupled to the differential input stage. The negative feedback control provides increased current gain in the second N-channel transistor, which drives a CMOS inverter to a full rail-to-rail voltage swing on its output.