发明名称 ANALOG MULTIPLIER
摘要 PROBLEM TO BE SOLVED: To suppress cross modulation distortion due to unnecessary higher harmonic distortion and distortion of an input signal which are unnecessary for output by equipping an analog multiplier composed of a CMOS with an adding circuit which supplies an addition/subtraction signal needed for multiplying operation without any distortion. SOLUTION: Respective unit circuits, i.e., a 1st adding circuit having a 1st MOS transistor(TR) composed of M4 and a 2nd MOS TR of M9, a 2nd adding circuit having a 1st MOS TR composed of M6 and a 2nd MOS TR of M10, a 3rd adding circuit having a 1st MOS TR composed of M7 and a 2nd MOS TR of M11, and a 4th adding circuit having a 1st MOS TR composed of M8 and a 2nd MOS TR of M12 are used to obtain a combination of two input signals and their inverted signals, i.e.. four addition/subtraction signals in total needed for analog multiplication without any distortion.
申请公布号 JPH10275193(A) 申请公布日期 1998.10.13
申请号 JP19970081055 申请日期 1997.03.31
申请人 TOSHIBA CORP 发明人 YAMAMOTO TAKESHI;KASAGI YOSHITAKA
分类号 G06G7/163;H03G3/10;(IPC1-7):G06G7/163 主分类号 G06G7/163
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