PHASE COMPARISON METHOD FOR DIGITAL SIGNAL, PHASE COMPARATOR CIRCUIT, PHASE COMPARISON METHOD IN THE PHASE COMPARATOR, PHASE COMPARATOR, PLL CIRCUIT, DATA DEMODULATION CIRCUIT AND DATA READ DEVICE

摘要

PROBLEM TO BE SOLVED: To provide the phase comparator in which phase comparison between a leading edge/a trailing edge of a reference signal and a detection timing point of a clock signal is attained and a lock state is stably maintained. SOLUTION: A synchronization circuit 28 detects a unidirectional change in a reference signal RIN based on a clock XCLK and provides an output of an inverted output signal XSG 11 and provides outputs of output signals SG12, SG13, based on succeeding clocks CLK, XCLK. A phase difference detection circuit 29 provides an output of a 1st phase difference detection signal, based on the reference signal RIN and the inverted output signal SG11, and provides an output of a 2nd phase difference signal, based on the output signals SG12, SG13. A phase difference arithmetic circuit 30 compares a phase at a leading edge/a trailing edge of the reference signal with a phase at a detection timing point of the clock signal based on the 1st and 2nd phase difference detection signals, the reference signal and a feedback signal FIN and provides an output of no UP/DOWN signal when the phases are matched.