| 摘要 |
PROBLEM TO BE SOLVED: To obtain a data relieving process that is shortened in the transfer time of a cache memory in case of a fault of a bus bridge unit, by connecting the bus bridge unit to processor units which process information. SOLUTION: A low-layer common bus 5 is provided with a memory control unit 2 and the bus bridge unit 4 is connected hierarchically to the memory control unit 2 through the low-layer common bus 5. Further, processor units 6a to 6n are connected to the bus bridge unit 4 through a high-layer common bus 8. If the bus bridge unit 4 gets out of order, the bus bridge unit 4 retrieves a cache tag 9 once detecting its fault. According to the retrieval, data in cache memories 7a to 7n are sent to a cache data part 10 to update the data of the cache data part 10, and a reset signal is outputted to the processor units 6a to 6n to make a fault recovery. |
