发明名称 CHIP-SIZE PACKAGE AND MANUFACTURE THEREOF
摘要 PROBLEM TO BE SOLVED: To eliminate the need of sealing by potting per product, mounting to or dismounting from carrying jigs to improve the mass productivity, by electrically connecting metal bumps on a chip to conductive patterns on a printed wiring board and fixing the chip to the wiring board. SOLUTION: Plated bumps 2a on a chip 2 are connected to a metal pattern 4a on a flexible board 4 through conductive grains 6a in an anisotropic conductive sheet 6, the metal pattern 4a is connected to a metal pattern 4b through interlayer conductive bumps 4c on the board 4, and the metal pattern 4b has mounting solder bumps. When the chip 2 is electrically connected to the board 4 through the sheet 6, it is also sealed to enhance the moisture resistance. This eliminates the need of the sealing by potting per product, and mounting to or dismounting from carrying jigs to improve the production efficiency.
申请公布号 JPH10270624(A) 申请公布日期 1998.10.09
申请号 JP19970075352 申请日期 1997.03.27
申请人 TOSHIBA CORP 发明人 OTSUKA MASASHI
分类号 H01L23/12;H01L21/56;H01L23/498;H01L23/50;(IPC1-7):H01L23/50;H01L25/07;H01L25/065;H01L25/18 主分类号 H01L23/12
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