发明名称 PHASE LOCKED LOOP DEVICE
摘要 PROBLEM TO BE SOLVED: To obtain a phase locked loop device in which no beat interference is caused in signals in the phase locked loop circuit with a simple circuit configuration and a phase noise characteristic is not deteriorated while making the phase locked loop device small. SOLUTION: A phase locked loop device is provided with a 1st phase locked loop (PLL) circuit 10a that provides an output of a 1st oscillation signal with a 1st frequency, a 2nd PLL circuit 10b that provides an output of a 2nd signal oscillated at a 2nd frequency not causing beat interference to the signal from the 1st PLL circuit 10a, a selection circuit 20 that selects the output signal from the 1st PLL circuit 10a or the output signal from the 2nd PLL circuit 10b and provides an output of a carrier signal, and a frequency conversion circuit 30 that is provided between the st PLL circuit 10a and the selection circuit 20 or between the 2nd PLL circuit 10b and the selection circuit 20 and converts the frequency of the 1st or 2nd signal into a frequency of the carrier signal.
申请公布号 JPH10271005(A) 申请公布日期 1998.10.09
申请号 JP19970070190 申请日期 1997.03.24
申请人 MITSUBISHI ELECTRIC CORP 发明人 SATO MASAHIKO
分类号 H03L7/22;H03L7/08;H04J3/00 主分类号 H03L7/22
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